1. Field of the Invention
The present invention relates to a driving circuit of a current-driven device for driving a current-driven device which is driven by supply of an electric current, a current-driven apparatus having this driving circuit and a current-driven device, and a method of driving this current-driven apparatus.
The present invention is applicable to an organic EL display, as well as such current-driven displays as an inorganic EL display and an LED, such current-driven memories as an MRAM, and driving circuits thereof.
2. Description of the Related Art
Current-driven apparatuses which are controlled in operation by electric currents supplied thereto have been developed heretofore. Among such current-driven apparatuses is an organic electro luminescence (EL) display.
With the advance of development, organic EL devices to be used in organic EL displays have improved in efficiency, contributing to reduced power consumption of the organic EL displays. The improved efficiency of the organic EL devices, however, makes the currents to be passed through the organic EL devices smaller, which requires a driving circuit for supplying (writing) the organic EL devices with these small currents accurately at speed. The inventors have formerly invented such a driving circuit, and disclosed it in Japanese Patent Laid-Open Publication No. 2003-195812.
FIG. 1 is a block diagram showing a conventional EL display described in Japanese Patent Laid-Open Publication No. 2003-195812. FIG. 2 is a circuit diagram showing a current source and a precharge circuit for each single data line, and a pixel circuit for each single pixel in the organic EL display shown in FIG. 1.
As shown in FIG. 1, the organic EL display 500 has a display unit 400. The display unit 400 is provided with a plurality (Y) of control lines 110 which extend in the horizontal direction, and a plurality (X) of data lines 120 which extend in the vertical direction. Pixels 100 are arranged at respective intersections of the control lines 110 and the data lines 120. Consequently, the display unit 400 has (X×Y) pixels 100 which are arranged in a matrix. Incidentally, when the organic EL display 500 is a color display, three adjoining pixels 100 arranged in the horizontal direction constitute a single group in which the pixels 100 emit light in red (R), blue (B), and green (G), respectively. The pixels 100 each have an organic EL device as its light-emitting device.
In addition, the organic EL display 500 has a vertical scanning circuit 300 which lies along a vertical side of the display unit 400 and is connected with the control lines 110. The vertical scanning circuit 300 selects the control lines 110 in succession. The organic EL display 500 also has a horizontal driving circuit 200 which lies along a horizontal side of the display unit 400 and is connected with the data lines 120. The horizontal driving circuit 200 supplies current signals to the pixels 100 that are connected to a control line 110 selected by the vertical scanning circuit 300. The light-emitting devices arranged in the pixels 100 have a proportional relationship between the currents supplied thereto and the luminances thereof. The currents supplied to the pixels 100 through the data lines 120 are adjusted in intensity so that the pixels 100 achieve display with tone levels. Note that the horizontal driving circuit 200 and the vertical scanning circuit 300 constitutes the driving circuit of the organic EL display 500.
As shown in FIG. 2, the horizontal driving circuit 200 is provided with a plurality (X) of current sources 220 for outputting current signals Iout to the respective data lines 120 of the display unit 400 (see FIG. 1). Precharge circuits 250 for precharging the data lines 120 are connected between the current sources 220 and the data lines 120.
Each pixel 100 has a pixel circuit in which a P-channel transistor T21 intended for current storage, a P-channel transistor T24 intended for switching, and a light-emitting device or organic EL device 130 are connected in series in this order between a supply voltage Ve1 and a ground potential GND. The gate of the current storing P-channel transistor T21 is connected to a data line 120 through N-channel transistors T22 and T23 intended for switching. The gates of the switching transistors T22 to T24 are connected to a control line 110. Besides, a capacitor C1 is arranged between the gate of the current storing transistor T21 and the supply voltage Ve1. The node between the switching transistors T22 and T23 is connected to the node between the current storing transistor T21 and the switching transistor T24, whereby the gate of the current storing P-channel transistor T21 is connected to the drain of the transistor T21 through the switching transistor T22. A parasitic capacitance Cp1 lies between the data line 120 and the ground potential.
Each precharge circuit 250 undergoes the supply voltage Ve1. For a potential generating circuit, a P-channel transistor T35 intended for driving and an N-channel transistor T31 intended for switching are connected in series in this order between the terminal to which the supply voltage Ve1 is applied and the current source 220. More specifically, either one of the source and drain (hereinafter, referred to as one terminal) of the N-channel transistor T31 is connected to the driving P-channel transistor T35. The other of the source and drain (hereinafter, referred to as the other terminal) is connected to the ground potential through the current source 220. Incidentally, the driving P-channel transistor T35 has the same size as that of the current storing P-channel transistor T21 of the pixel 100. The two transistors thus have substantially the same characteristics. The precharge circuit 250 also has N-channel transistors T32 and T33 and a P-channel transistor T34 which are intended for switching. The gates of these switching transistors T31 to T34 are connected to wiring 252. A precharge signal PC2 is input to the wiring 252 from exterior.
Then, the node A between the driving P-channel transistor T35 and the switching N-channel transistor T31 is connected to one terminal of the N-channel transistor T33 intended for switching. The other terminal of this transistor T33 is connected to the gate of the driving P-channel transistor T35. A voltage follower amplifier 251 is arranged between the node A and the switching transistor T32. The node A is connected to the noninverting input terminal of this voltage follower amplifier 251. The output of the amplifier 251 is connected to one terminal of the transistor T32 and the inverting input terminal of the amplifier 251. The other terminal of the transistor T32 is connected to the data line 120. Moreover, one terminal of the switching P-channel transistor T34 is connected to the current source 220. The other terminal of the transistor T34 is connected to the data line 120.
Next, description will be given of the operation of the organic EL display which is configured as described above. Initially, the vertical scanning circuit 300 shown in FIG. 1 scans the control lines 110. More specifically, the vertical scanning circuit 300 selects the first control line 110 to the Yth control line 110 in succession, applying a signal of high level to the selected control line 110.
Then, the current sources 220 in the horizontal driving circuit 200 output the current signals to the respective data lines 120. At this time, the horizontal driving circuit 200 passes currents corresponding to the tone levels to be displayed on the pixels 100 that are connected to the control line 110 selected by the vertical scanning circuit 300, through the data lines 120 in connection with the pixels 100. Consequently, as shown in FIG. 2, the current signal Iout is supplied to the switching N-channel transistor T31 and the switching P-channel transistor T34 in each precharge circuit 250. If the precharge signal PC2 is not selected, i.e., at low level, the switching N-channel transistors T31 and T32 turn off and the switching P-channel transistor T34 turns on. The current signal Iout is thus supplied from the current source 220 to the data line 120 through the transistor T34. In this way, the horizontal driving circuit 200 outputs the current signals Iout to the data lines 120.
In each of the pixels 100 that are selected by the vertical scanning circuit 300 (see FIG. 1), the signal of high level, indicating selection, is applied to the control line 110. This turns on the switching N-channel transistors T22 and T23. As a result, the data line 120 is connected to the gate of the current storing P-channel transistor T21 and one end of the capacitor C1 through the transistors T23 and T22. Moreover, the switching P-channel transistor T24 is turned off. This determines the amount of the current to flow through the current storing P-channel transistor T21, and charges the capacitor C1. The pixel 100 is thus written with the current signal Iout.
Then, the vertical scanning circuit 300 scans the next control line, and the potential of the control line 110 shown in FIG. 2 is switched from high level (selected) to low level (not selected). Then, the switching N-channel transistors T22 and T23 turn off, and the switching P-channel transistor T24 turns on. As a result, the current path consisting of a series connection of the current storing P-channel transistor T21, the switching P-channel transistor T24, and the organic EL device 130 in this order is formed from the supply voltage Ve1 to the ground potential GND independent of the data line 120. More specifically, the supply voltage Ve1 is applied to one terminal of the current storing P-channel transistor T21. The other terminal of this transistor T21 is connected to one terminal of the switching P-channel transistor T24. The other terminal of this transistor T24 is connected to the input terminal of the organic EL device 130. The output terminal of this organic EL device 130 is subjected to the ground potential GND. As a result, the current written in the current storing P-channel transistor T21 flows through this current path, and the organic EL device 130 emits light at a tone level corresponding to this current. In this case, the capacitor C1 maintains the gate potential of the current storing P-channel transistor T21 at a constant value. The amount of the current flowing through the transistor T21 is thus maintained at a constant value, so that the luminance of the organic EL device 130 is maintained at a predetermined tone level.
The vertical scanning circuit 300 thus scans the control lines 110 to select the Y control lines 110 one by one in succession. Upon each selection, the horizontal driving circuit 200 outputs the current signals Iout corresponding to intended tone levels to the pixels 100 that are in connection with the control line 110 selected by the vertical scanning circuit 300. An image is displayed on the display unit 400 in this way.
As above, the display unit 400 can theoretically display images without the precharge circuits 250. Nevertheless, since the data lines 120 are accompanied with the parasitic capacitances Cp1, the parasitic capacitances Cp1 must be charged and discharged each time the potentials of the data lines 120 are changed. Setting the data lines 120 to a desired value of potential thus requires a certain amount of write time. Besides, the smaller the current signals Iout to be supplied to the data lines 120 are, the longer the write time becomes. Meanwhile, in order to display flicker-free images to viewers, the vertical scanning circuit 300 must scan the control lines 110 at or above a certain speed. This means an upper limit to the duration for each single control line 110 to be selected for. On this account, excessive write time can result in insufficient write operations, with the problem of degraded image quality.
Then, in the conventional example described in Japanese Unexamined Patent Application Publication No. 2003-195812, the precharge circuits 250 are provided between the current sources 220 and the data lines 120. As shown in FIG. 2, in each of the precharge circuits 250, the precharge signal PC2 is switched to high level (selected) immediately after a new control line 110 is selected. Consequently, the switching N-channel transistors T31 to T33 turn on, and the switching P-channel transistor T34 turns off. As a result, the current signal Iout output from the current source 220 is supplied to the driving P-channel transistor T35 through the transistors T31 and T33. This determines the amount of the current to flow through the driving P-channel transistor T35, and sets the potential of the node A to a potential corresponding to the current signal Iout. Incidentally, the transistor T35 has substantially the same size and characteristics as those of the transistor T21 in each pixel 100. The potential of the node A mentioned above thus becomes substantially the same as that of the gate of the transistor T21 when the current signal Iout is applied to the transistor T21. Then, the potential of the node A is applied to the noninverting input terminal of the voltage follower amplifier 251, and the same potential as that of the node A is output from the output terminal of the voltage follower amplifier 251 to the data line 120. The voltage follower amplifier 251 has a high capability for current supply, and can thus charge and discharge the parasitic capacitance Cp1 of the data line 120 quickly. That is, because of the provision of the precharge circuit 250, the potential of the data line 120 can be set to a potential corresponding to the current signal Iout more quickly than when no precharge circuit 250 is provided.
Subsequently, the precharge signal PC2 is switched to low level (unselected), and the current signal Iout is supplied directly to the data line 120. At this time, the data line 120 is already given a potential close to the target value by the foregoing operation of the precharge circuit 250, and the current signal Iout has only to correct a precharge-time error in the potential of the data line 120. This correction requires not much time. As a result, it is possible to reduce the write time of the pixel 100. Incidentally, the precharge-time error in the potential of the data line 120 occurs due to an input offset voltage of the voltage follower amplifier 251 and characteristic differences between the driving P-channel transistor T35 and the driving P-channel transistor T21.
The foregoing conventional technique, however, has the following problems. As shown in FIG. 2, in each precharge circuit 250, parasitic capacitances arise between the wiring for the current signal Iout to flow through and the ground potential. More specifically, the wiring from the transistor T35 to the noninverting input terminal of the voltage follower amplifier 251 is accompanied with a parasitic capacitance Cp2. The wiring from the current source 220 to the transistors T31 and T34 is accompanied with a parasitic capacitance Cp3. Incidentally, the parasitic capacitance Cp2 consists chiefly of the gate capacitor of the driving P-channel transistor T35 when the switching N-channel transistor T33 is on, and the input capacitor of the voltage follower amplifier 251. The parasitic capacitance Cp3 consists chiefly of capacitors occurring between the laid wiring and other wiring. These parasitic capacitances Cp2 and Cp3 are smaller than the parasitic capacitance Cp1 of the data line 120. Nevertheless, these parasitic capacitances Cp2 and Cp3 increase the settling time to elapse between when the precharge signal PC2 is selected, or switched to high level, and when the precharge output potential, or the potential applied to the noninverting input terminal of the voltage follower amplifier 251, converges to a certain value. The reason for this is that the parasitic capacitances Cp2 and Cp3 must be charged and discharged each time the value of the current signal Iout is changed.
FIG. 3 is a chart for showing the effect of the current signal Iout on the settling time of the input potential of the voltage follower amplifier. In the chart, the abscissa indicates the intensity of the current signal Iout, and the ordinate the settling time of the input potential of the voltage follower amplifier. Incidentally, “ΔV” shown in FIG. 3 represents a variation in the input potential of the voltage follower amplifier. The potential variation ΔV shows a difference between the potential of the data line 120 when a control line 110 is selected and the potential of the data line 120 when the next control line 110 is selected.
As shown in FIG. 3, the lower the intensity of the current signal Iout is, the longer the settling time of the input potential of the voltage follower amplifier becomes. In a pixel that emits light of a lower tone level, i.e., darker tone level, the smaller current signal Iout can make the settling time extremely longer. With a level-zero display, or black display, the settling time reaches its maximum. In addition, with recent improvements to the efficiency of the organic EL device, the current signal Iout decreases accordingly. The settling time of the input potential of the voltage follower amplifier is thus becoming increasingly long. Moreover, the greater the potential variation ΔV is, the longer the settling time of the input potential of the voltage follower amplifier becomes. This is equivalent to the case, for example, where the current signal Iout has a higher intensity when a control line 110 is selected, and the current signal Iout has a lower intensity when the next control line 110 is selected.
The longer settling time of the input potential of the voltage follower amplifier then increases the time necessary for precharge. This accordingly decreases the time for outputting the current signal Iout directly to the pixel 100, thereby hindering sufficient correction on precharge-time errors in the potentials of the data line 120. Consequently, the accuracy in writing the current signal Iout to the pixel 100 lowers with a drop in image quality. Specifically, trailing defects can occur from writing failures, for example.